The invention relates to the field of memory devices, for example semi-conductor memory devices such as DRAM, SRAM or Flash-EEPROM. The invention relates to a memory device and an interface to a host system for optimized data transfer between the memory device and the host system comprising said memory device.
A known memory device comprises a plurality of memory cells and may comprise some integrated circuits to perform some basic functions of the memory device such as mapping addresses to memory cells, hiding defective memory cells from further use or the like. The memory device may be integrated on a single semi-conductor die or a plurality of semi-conductor dies assembled in a single package. Some or more of these packages or dies may be assembled on a printed circuit board.
Memory devices are commonly used in electronic systems incorporating digital electronics, such as personal computers, music players, digital cameras, networking servers, routers or the like. An electronic system comprising said memory device is hereinafter referred to as host system. A memory device may be inserted into the host system as a separate module or may be integrated on the same printed circuit board. Usually, the host system comprises a microprocessor to perform its basic tasks. Furthermore, the host system comprises a memory control unit, either integrated into the microprocessor, integrated into the memory device or as a stand-online device. The memory control unit is configured to establish and control an interface between at least one memory device and the host system.
Physically, the interface may comprise a plurality of transmission lines. A subset of these transmission lines may be combined to form a data bus, another subset of transmission lines may form an address bus and a further subset of transmission lines may constitute a command bus.
The host system and the memory device are synchronized by a common clock signal. To perform read- or write-operations on the memory device, the memory control unit specifies the address of at least one memory cell and transmits this address and the respective command and the data if needed to the memory device where the command is executed by writing the data to the specified address or reading data from the specified address and delivering it to the host system.
To perform any operation on data stored in the memory device, the memory control unit has to perform a read-operation to make said data available to the micro processor of the host system. In the next step, the micro processor may perform an operation on said data. The result of said operation is transferred by a write command performed by said memory control unit to the memory device. This procedure leads to a high load on the interface between the host system and the memory device.
Therefore, there is a need to optimize the data transfer between the memory device and the host system.